1. Field of Invention
This invention relates to circuit improvements, and more particularly to methods and circuits for reducing leakage currents in circuits.
2. Relevant Background
A strong correlation has been shown to exist between the input vector applied to a logic cell and the leakage current through it. For example, for a 2-input static AND cell, it has been reported that the total drain to source leakage current when both the inputs are at logic 1 is 50 times greater than when the inputs are at logic 0.
As process technologies continue to scale, leakage power becomes an increasingly important part of the total power dissipation of the chip. This is as threshold voltages and gate lengths are reduced in finer geometry processes, leading to increased leakage current. In addition, with significant gate oxide scaling, leakage current starts to occur through the transistor gates. Leakage power is especially crucial in portable devices, such as cell phones, where it can directly affect the operating time before which the device needs to be recharged.
One solution that has been proposed is to determine whether a logic 1 or logic 0 value at the gate of a particular device is likely to minimize leakage of the device. Then, a vector is loaded into the latches of the circuit where leakage power dissipation is to be minimized. Thus, the latches apply a logic 1 or logic 0 value, as needed. This may be, for example, in response to a “standby” signal applied to or generated by the circuit.
As integrated circuits become increasingly complex, mechanisms for testing have been designed into the circuits. A typical testing mechanism is a “scan-chain”. A scan chain typically includes a linked set of flip-flops, and usually, serially provided data is introduced into a flip-flop at one end of the chain and is clocked sequentially into the scan chain, over a number of clock cycles. The scan chain applies the test input (TI) data to various circuit elements, which produce a known output if operating correctly. If an output other than the expected known output is produced, an error in the circuit is indicated. The set of TI data that is clocked into the scan chain is often referred to as a vector, and, more particularly, is referred to herein as a test vector.
The flip-flops are configurable to accept either the test vector in a test mode or data in a normal operating mode. Thus, a test enable (TE) signal is accepted by the flip-flops of the scan chain to essentially multiplex either the test vector or the actual data for application to the circuit.
Another technique to reduce leakage power is to use large shut-off transistors which are provided to the power source. This technique requires significant layout overhead and also leads to power supply integrity issues.